Regviz

Freescale Semiconductor /MK30D7 /ADC0 /SC2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SC2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MK30D7/ADC1/SC2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)REFSEL 0 (0)DMAEN 0 (0)ACREN 0 (0)ACFGT 0 (0)ACFE 0 (0)ADTRG 0 (0)ADACT

DMAEN=0, REFSEL=00, ADACT=0, ACFGT=0, ADTRG=0, ACFE=0, ACREN=0

Description

Status and control register 2

Fields

REFSEL

Voltage reference selection

0 (00): Default voltage reference pin pair (external pins VREFH and VREFL)

1 (01): Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internal sources depending on MCU configuration. Consult the Chip Configuration information for details specific to this MCU.
DMAEN

DMA enable

0 (0): DMA is disabled.

1 (1): DMA is enabled and will assert the ADC DMA request during a ADC conversion complete event noted by the assertion of any of the ADC COCO flags.
ACREN

Compare function range enable

0 (0): Range function disabled. Only the compare value 1 register (CV1) is compared.

1 (1): Range function enabled. Both compare value registers (CV1 and CV2) are compared.
ACFGT

Compare function greater than enable

0 (0): Configures less than threshold, outside range not inclusive and inside range not inclusive functionality based on the values placed in the CV1 and CV2 registers.

1 (1): Configures greater than or equal to threshold, outside range inclusive and inside range inclusive functionality based on the values placed in the CV1 and CV2 registers.
ACFE

Compare function enable

0 (0): Compare function disabled.

1 (1): Compare function enabled.
ADTRG

Conversion trigger select

0 (0): Software trigger selected.

1 (1): Hardware trigger selected.
ADACT

Conversion active

0 (0): Conversion not in progress.

1 (1): Conversion in progress.

Links

()

Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data